This attribute consists of a list of all the layers in the current EDA design. Name: .all_eda_layers
.all_eda_layers
All EDA Layers
cell
Indicates whether it is allowed to remove nonfunctional pads. Name: .allowed_to_remove_non_functional_pads
.allowed_to_remove_non_functional_pads
Allowed to Remove nonfunctional Pads
cell
Assigned to a drill to define the maximum annular ring size between the drill and the copper of the bottom layer of the drill span. Name: .ar_pad_drill_bottom_max
.ar_pad_drill_bottom_max
Max Pad AR Drill Bottom
object
Assigned to a drill to define the minimum annular ring size between the drill and the copper of the bottom layer of the drill span. Name: .ar_pad_drill_bottom_min
.ar_pad_drill_bottom_min
Min Pad AR Drill Bottom
object
Assigned to a drill to define the maximum annular ring size between the drill and the copper of an inner layer in the drill span. Name: .ar_pad_drill_inner_max
.ar_pad_drill_inner_max
Max Pad AR Drill Inner
object
Assigned to a drill to define the minimum annular ring size between the drill and the copper of an inner layer in the drill span. Name: .ar_pad_drill_inner_min
.ar_pad_drill_inner_min
Min Pad AR Drill Inner
object
Assigned to a drill to define the maximum annular ring size between the drill and the top copper layer in the drill span. Name: .ar_pad_drill_top_max
.ar_pad_drill_top_max
Max Pad AR Drill Top
object
Assigned to a drill to define the minimum annular ring size between the drill and the top copper layer in the drill span. Name: .ar_pad_drill_top_min
.ar_pad_drill_top_min
Min Pad AR Drill Top
object
Assigned to a drill piercing the bottom layer, to define the maximum annular ring size between the drill and the soldermask on the bottom layer. Name: .ar_sm_drill_bottom_max
.ar_sm_drill_bottom_max
Max SM AR Drill Bottom
object
Assigned to a drill piercing the bottom layer, to define the minimum annular ring size between the drill and the soldermask on the bottom layer. Name: .ar_sm_drill_bottom_min
.ar_sm_drill_bottom_min
Min SM AR Drill Bottom
object
Assigned to a drill piercing the top layer, to define the maximum annular ring size between the drill and the soldermask on the top layer. Name: .ar_sm_drill_top_max
.ar_sm_drill_top_max
Max SM AR Drill Top
object
Assigned to a drill piercing the top layer, to define the minimum annular ring size between the drill and the soldermask on the top layer. Name: .ar_sm_drill_top_min
.ar_sm_drill_top_min
Min SM AR Drill Top
object
Assigned to a drill piercing the bottom layer, to define the maximum annular ring size between the drilled pad of the bottom layer and the soldermask above. Name: .ar_sm_pad_bottom_max
.ar_sm_pad_bottom_max
Max SM AR Bottom
object
Assigned to a drill piercing the bottom layer, to define the minimum annular ring size between the drilled pad of the bottom layer and the soldermask above. Name: .ar_sm_pad_bottom_min
.ar_sm_pad_bottom_min
Min SM AR Bottom
object
Assigned to a drill piercing the top layer, to define the maximum annular ring size in between the drilled pad of the top layer and the soldermask above. Name: .ar_sm_pad_top_max
.ar_sm_pad_top_max
Max SM AR Top
object
Assigned to a drill piercing the top layer, to define the minimum annular ring size in between the drilled pad of the top layer and the solder mask above. Name: .ar_sm_pad_top_min
.ar_sm_pad_top_min
Min SM AR Top
object
DFx Area Name Name: .area_name
.area_name
DFx Area Name
object
If YES, this job is a multipanel array, with the same panel possibly appearing in 180 - degree rotation to itself Name: .array_with_rotation
.array_with_rotation
Array with Rotation
cell
Indicating to which entity the feature belongs (component, package, net, board) Name: .artwork
Used with layer type DIELECTRIC to indicate that a metal layer is to be manufactured on top of the DIELECTRIC material. (optional) Name: .attrfab_copper_layer_above
.attrfab_copper_layer_above
Copper Layer Above
layer
Used with layer type DIELECTRIC to indicate that a metal layer is to be manufactured on bottom of the DIELECTRIC material. (optional) Name: .attrfab_copper_layer_below
.attrfab_copper_layer_below
Copper Layer Below
layer
Customer part number. Name: .attrfab_cpn
.attrfab_cpn
Customer PN (CPN)
component
A text field that is intended to carry the material name as reference in the design application. (optional) Name: .attrfab_dielectric_material
.attrfab_dielectric_material
Dielectric Material
layer
Unlimited number of descriptions. Name: .attrfab_dsc
.attrfab_dsc
Descriptions (DSC)
component
Internal part number. Name: .attrfab_ipn
.attrfab_ipn
Internal PN (IPN)
component
Defines the layer as either rigid or flexible.
Default: rigid Name: .attrfab_layer_form
.attrfab_layer_form
Layer Form (Rigid or Flexible)
layer
Points to information stored in the bom files. The LNFILE line provides the line number and the file name. For example, LNFILE 5 Rev13.v1 indicates that information is stored in line 5 of file Rev13.v1 Name: .attrfab_lnfile
.attrfab_lnfile
LNFILE
component
The MPN lines contain these parameters separated by spaces: * qualify status — Whether the part(vendor + mpn) is qualified for production: -1: Not qualified, 0: Unknown, 1: Qualified. * chosen status — Whether the part is chosen from among the alternate parts for the CPN. Only one part can be a chosen part. 0: Not chosen, 1: Chosen MPN — The manufacturer part number. For example, MPN 0 Y 4N35S for a CPN component whose qualification is unknown(0), that is the chosen component(1), with a manufacturer part number of 4N35S. Name: .attrfab_mpn
.attrfab_mpn
Manufacturer PN (MPN)
component
Alternate 1: The MPN lines contain these parameters separated by spaces: * qualify status — Whether the part(vendor + mpn) is qualified for production: -1: Not qualified, 0: Unknown, 1: Qualified. * chosen status — Whether the part is chosen from among the alternate parts for the CPN. Only one part can be a chosen part. 0: Not chosen, 1: Chosen MPN — The manufacturer part number. For example, MPN 0 Y 4N35S for a CPN component whose qualification is unknown(0), that is the chosen component(1), with a manufacturer part number of 4N35S. Name: .attrfab_mpn_1
.attrfab_mpn_1
Alt. 1: Manufacturer PN (MPN)
component
Alternate 2: The MPN lines contain these parameters separated by spaces: * qualify status — Whether the part(vendor + mpn) is qualified for production: -1: Not qualified, 0: Unknown, 1: Qualified. * chosen status — Whether the part is chosen from among the alternate parts for the CPN. Only one part can be a chosen part. 0: Not chosen, 1: Chosen MPN — The manufacturer part number. For example, MPN 0 Y 4N35S for a CPN component whose qualification is unknown(0), that is the chosen component(1), with a manufacturer part number of 4N35S. Name: .attrfab_mpn_2
.attrfab_mpn_2
Alt. 2: Manufacturer PN (MPN)
component
BOM Package name (PKG). Name: .attrfab_pkg
.attrfab_pkg
BOM Package (PKG)
component
Part Priority. 1: is Top priority 2: Second priority 3:Third priority...so forth 0: Unknown Name: .attrfab_priority
.attrfab_priority
PRIORITY
component
Alternate 1: Part Priority. 1: is Top priority 2: Second priority 3:Third priority...so forth 0: Unknown Name: .attrfab_priority_1
.attrfab_priority_1
Alt. 1: PRIORITY
component
Alternate 2: Part Priority. 1: is Top priority 2: Second priority 3:Third priority...so forth 0: Unknown Name: .attrfab_priority_2
.attrfab_priority_2
Alt. 2: PRIORITY
component
QLF Name: .attrfab_qlf
.attrfab_qlf
QLF
component
Establishes a connection between Silk/Paste/Mask and Metal layers for Flex and Rigid-Flex designs. (optional) Name: .attrfab_reference_layer
MPN from an external vendor part library corresponding to original MPN(as determined in BOM Validation). Name: .attrfab_vpl_mpn
.attrfab_vpl_mpn
VPL Manufacturer PN (VPL_MPN)
component
Alternate 1: MPN from an external vendor part library corresponding to original MPN(as determined in BOM Validation). Name: .attrfab_vpl_mpn_1
.attrfab_vpl_mpn_1
Alt. 1: VPL Manufacturer PN (VPL_MPN)
component
Alternate 2: MPN from an external vendor part library corresponding to original MPN(as determined in BOM Validation). Name: .attrfab_vpl_mpn_2
.attrfab_vpl_mpn_2
Alt. 2: VPL Manufacturer PN (VPL_MPN)
component
Manufacturer from an external vendor part library corresponding to original vendor(as determined in BOM Validation). Name: .attrfab_vpl_vnd
.attrfab_vpl_vnd
VPL Manufacturer (VPL_VND)
component
Alternate 1: Manufacturer from an external vendor part library corresponding to original vendor(as determined in BOM Validation). Name: .attrfab_vpl_vnd_1
.attrfab_vpl_vnd_1
Alt. 1: VPL Manufacturer (VPL_VND)
component
Alternate 2: Manufacturer from an external vendor part library corresponding to original vendor(as determined in BOM Validation). Name: .attrfab_vpl_vnd_2
.attrfab_vpl_vnd_2
Alt. 2: VPL Manufacturer (VPL_VND)
component
Defines the angle at which a board is inserted into a 5DX machine. Values are translated as 0, 90, 180, 270 degrees. Name: .axi_direction
.axi_direction
Assembly X-Ray Inspection Direction
cell
Used by Backdrill Analysis to indicate the layer not to be penetrated during the backdrill process. Name: .backdrill_penetrate_stop_layer
.backdrill_penetrate_stop_layer
Backdrill not Penetrate Layer Name
layer
Contains the drill designator that is to be used for each tool. Name: .bit
.bit
Drill Designator
object
bbm: Bad board mark. Skip inspection of the step.
gpm: good panel mark. The panel can be accepted for printing without scanning its steps for bad board marks. Name: .board_mark
.board_mark
VI Tech. Board Mark
object
Total thickness of the board. Name: .board_thickness
.board_thickness
Board Thickness
product
0
Name of Wire Bond Name: .bond_name
.bond_name
Name of Wire Bond
object
Name of the bonding profile. Name: .bonding_profile
.bonding_profile
Bonding profile
object
Assigned to a symbol that represents a break-away that can be inserted into any line or arc of the rout path. Name: .break_away
.break_away
Rout Break Away
symbol
no
Assigned to a pad or a point in a break-away symbol (that was given the attribute .break_away). Name: .brk_point
.brk_point
Rout Break Point
object
no
The nano-ohmic resistance of the semiconductor material. Name: .bulk_resistivity
.bulk_resistivity
Bulk Resistivity (nano-ohm)
layer
0.0
Indicates whether there has been a local change to a pad code in the local design. Name: .cad_local_footprint_change
.cad_local_footprint_change
CADStar Pad Change
component|package
no
Contains the full CAD package name of a Cadstar component. Name: .cad_package_name
.cad_package_name
CADStar Package Name
component
Assigns component properties in accordance with data received from the ASSY_PN_OVERRIDE property. Name: .cad_part_override
.cad_part_override
CAD Part Varient Support
component|package
Specifies component is expected to have a fiducial at its center. Name: .center_fiducial
.center_fiducial
Center Fiducial Required
component|package
no
Specifies the x-offset from the CAD centroid to the calculated package centroid. Name: .centroid_correction_x
.centroid_correction_x
Centroid Correction X
component|package
0
Specifies the y-offset from the CAD centroid to the calculated package centroid. Name: .centroid_correction_y
.centroid_correction_y
Centroid Correction Y
component|package
0
Can be attached to any feature or component to define the color to be used in plotting a layer in HPGL-1 or 2. The format is rrggbb (where r = red, g = green, b = blue). Name: .color
.color
HPGL Output Color
component|object
Used for general textual comments. Name: .comment
.comment
Comment
all
For a chained feature, this attribute sets the offset of the cutting tool from the rout path. Name: .comp
.comp
Rout Compensate
object
none
Stores the height of the component above the board surface. Name: .comp_height
.comp_height
Component Height
object|component|package
0.0
This attribute is used to assign the same ID to a component under which there is an area with space for a shorter component, and to the feature that defines the area. Name: .comp_height_area
.comp_height_area
Allegro Height ID
component|object
The height of the tallest package (in the CPN package of alternate MPNs) above the board surface. Name: .comp_height_max
.comp_height_max
Maximal Height
component|package
Contains the minus tolerance for component height, used for calculation of plug-in boards. Name: .comp_htol_minus
.comp_htol_minus
Height Tolerance Minus
component|package
Contains the plus tolerance for component height, used for calculation of plug-in boards. Name: .comp_htol_plus
.comp_htol_plus
Height Tolerance Plus
component|package
This attribute, when set, disables spacing checks on a component during assembly analysis. It is used for printed components that have no actual body Name: .comp_ign_spacing
.comp_ign_spacing
Ignore during Spacing Analysis
component|package
no
Determines whether the component is to be ignored when calculating statistics, or during certain operations, such as analysis. Name: .comp_ignore
.comp_ignore
Ignore Component
component|package
no
Indicates whether the component is a surface mount, through-hole mount, press-fit or other. Name: .comp_mount_type
.comp_mount_type
Mount Type
component|package
Name of the die component on the HDI technology layer. Name: .comp_name
.comp_name
Name of Die Component
component
POLARIZED, has a specific pin designated as pin #1. NON_POLARIZED has no specific pin #1. Name: .comp_polarity
.comp_polarity
Component Polarity
component|package
Component Type 1 Name: .comp_type
.comp_type
Type 1
component|package
Component Type 2 Name: .comp_type2
.comp_type2
Type 2
component|package
Consists of a list of variants where a component is used. The list contains variant names separated by a colon (:) Name: .comp_variant_list
.comp_variant_list
Variant List
component|package
Stores the weight of the component. Name: .comp_weight
.comp_weight
Component Weight
component|package
The weight of copper according to its Units of Measurement. Name: .copper_weight
Assigned to the mid-point of a netlist to force it to become a testpoint. If both.non_tp and.critical_tp are assigned to the same point, .critical_tp takes precedence and the mid point is tested. In case of a drilled feature the attribute must be added to the drill hole. Name: .critical_tp
.critical_tp
Netlist Critical Midpoint Output
object
no
Consists of the name of the current variant for a step. Name: .current_variant
.current_variant
Current Variant
cell
This attribute can store the name of the customer for whom the product model was created. Name: .customer
.customer
Customer
product
Assigned to lines added in the creation of film layers by the film optimization algorithm. Name: .cut_line
.cut_line
Film Optimization Cut Line
object
The source of the data. For example, Cadence, Mentor. Name: .data_source
.data_source
Data Source
product|cell
BOM Description field 1 Name: .desc1
.desc1
BOM Description 1
component|package
BOM Description field 10 Name: .desc10
.desc10
BOM Description 10
component|package
BOM Description field 2 Name: .desc2
.desc2
BOM Description 2
component|package
BOM Description field 3 Name: .desc3
.desc3
BOM Description 3
component|package
BOM Description field 4 Name: .desc4
.desc4
BOM Description 4
component|package
BOM Description field 5 Name: .desc5
.desc5
BOM Description 5
component|package
BOM Description field 6 Name: .desc6
.desc6
BOM Description 6
component|package
BOM Description field 7 Name: .desc7
.desc7
BOM Description 7
component|package
BOM Description field 8 Name: .desc8
.desc8
BOM Description 8
component|package
BOM Description field 9 Name: .desc9
.desc9
BOM Description 9
component|package
The design center from which the product model originated. Name: .design_center
.design_center
Design Center
product|cell
Defines the design origin x coordinate. Name: .design_origin_x
.design_origin_x
Design X Origin
product
0
Defines the design origin y coordinate. Name: .design_origin_y
.design_origin_y
Design Y Origin
product
0
This attribute is an enhancement of .device_type and is used to store the style of the component as defined in GenCAD (such as, NPN, PNP, NFET, PFET, NJFET, PJFET, TTL, CMOS and ECL). Name: .device_style
.device_style
Device Style
component|package
Stores the type of the component as defined in the device(such as, RES, VRES, DIODE, ZENER, LOGIC, SWITCH, CONN, etc.). Name: .device_type
.device_type
Device Type
component|package
Stores the electrical value of a component. Name: .device_value
.device_value
Device Electrical Value
component|package
This is a real value expressing the percent of the value to use as a tolerance (negative tolerance). This is used for all devices. Range of characters : all floating point numbers. Name: .device_value_ntol
.device_value_ntol
Device Value Negative Tolerance
component|package
0.0
This is a real value expressing the percent of the value to use as a tolerance (positive tolerance). This is used for all devices. Range of characters : all floating point numbers. Name: .device_value_ptol
.device_value_ptol
Device Value Positive Tolerance
component|package
0.0
The ratio of the field without dielectric(Eo) to the net field(E) with dielectric. It is unitless and has a range value of 1 for metals. Typical values are 4 and 5.
(0.0 to 1000.0; default = 0.0) Name: .dielectric_constant
.dielectric_constant
Dielectric Constant (ER)
layer
0.0
Differential pair name associating two nets that must be routed together. Name: .diff_pair
.diff_pair
Differential Pair
net
Spacing gap value specifying the spacing between differential pair nets. Name: .dpair_gap
.dpair_gap
Differential Pair Spacing
net
Specifies whether the keepout/keepin area applies to Top, Bottom, or Both component layers. Name: .drc_assembly_lyrs
.drc_assembly_lyrs
Assigned Area to Component Side
object
Assigned to a DRC area defined for the whole board. Name: .drc_board
.drc_board
Analysis Board Area
object
Assigns component height restriction to a keepin/keepout area. Name: .drc_comp_height
.drc_comp_height
Component Height for Area
object
Stores name of document layer in which all component height restriction keepin/keepout areas are stored. Name: .drc_comp_height_lyr
.drc_comp_height_lyr
Comp. Height Restriction Layer
product
Defines an area as the board's component placement keepin boundary. Name: .drc_comp_keepin
.drc_comp_keepin
Component Keep In
object
Stores name of document layer in which all component keepin areas are stored. Name: .drc_comp_keepin_lyr
.drc_comp_keepin_lyr
Component Keep In Layer
product
Defines an area as the board's component placement keepout boundary. Name: .drc_comp_keepout
.drc_comp_keepout
Component Keep Out
object
Stores name of document layer in which all component keepout areas are stored. Name: .drc_comp_keepout_lyr
.drc_comp_keepout_lyr
Component Keep Out Layer
product
Value=layer names separated by semi-colons(;). User-defined attribute for user to specify name of layers in which to activate keepin / keepout areas Name: .drc_etch_lyrs
.drc_etch_lyrs
DFx Area Layers by Name
object
Defines a keepin/keepout area as effective on all layers. Name: .drc_etch_lyrs_all
.drc_etch_lyrs_all
DFx Area All Layers
object
Values=string consisting of 0 and 1 characters. Allows the keepin/keepout area to apply only to specified board layers. The attribute's length is equal to the number of board layers. 0=ignore layer, 1=activate areas in that layer. Name: .drc_etch_lyrs_bit
.drc_etch_lyrs_bit
DFx Area Selected Layers
object
Stores the maximum height of components to be allowed in a height restriction area. Name: .drc_max_height
.drc_max_height
Maximum Height
object
Analysis Mechanical Area Name: .drc_mech
.drc_mech
Analysis Mechanical Area
object
Stores the minimum height of components to be allowed in a height restriction area. Name: .drc_min_height
.drc_min_height
Minimum Height
object
Specifies area to be used as pads keepout boundary. Name: .drc_pad_keepout
.drc_pad_keepout
Pad Keep Out
object
Stores name of document layer in which all pad keepout areas are stored. Default as defined in the drc_pad_keepout configuration parameter. Name: .drc_pad_keepout_lyr
.drc_pad_keepout_lyr
Pad Keep Out Layer
product
Specifies area to be used as planes keepout boundary. Name: .drc_plane_keepout
.drc_plane_keepout
Plane Keep Out
object
Stores name of document layer in which all plane keepout areas are stored. Name: .drc_plane_keepout_lyr
.drc_plane_keepout_lyr
Plane Keep Out Layer
product
Assigned to DRC areas defined for components. Name: .drc_ref_des
.drc_ref_des
Analysis Reference Designator
object
Specifies areas to be used as the rout keepin boundary (rout = lines, arcs, vias, pads and surfaces on signal and/or power and ground layers). Name: .drc_route_keepin
.drc_route_keepin
Route Keep In
object
Stores name of document layer in which all rout keepin areas are stored. Name: .drc_route_keepin_lyr
.drc_route_keepin_lyr
Route Keep In Layer
product
Specifies areas to be used as the rout keepout boundary (rout = lines, arcs, vias, pads and surfaces on signal and/or power and ground layers). Name: .drc_route_keepout
.drc_route_keepout
Route Keep Out
object
Stores name of document layer in which all rout keepout areas are stored. Name: .drc_route_keepout_lyr
.drc_route_keepout_lyr
Route Keep Out Layer
product
Defines areas to be used as testpoint keepin area boundaries. Name: .drc_tp_keepin
.drc_tp_keepin
Testpoint Keep In
object
Stores name of document layer in which all testpoint keepin areas are stored. Name: .drc_tp_keepin_lyr
.drc_tp_keepin_lyr
Testpoint Keep In Layer
product
Defines areas to be used as testpoint keepout area boundaries. Name: .drc_tp_keepout
.drc_tp_keepout
Testpoint Keep Out
object
Stores name of document layer in which all testpoint keepout areas are stored. Name: .drc_tp_keepout_lyr
.drc_tp_keepout_lyr
Testpoint Keep Out Layer
product
Defines areas to be used as trace keepout boundaries (traces=lines and arcs on signal and/or power and ground layers). Name: .drc_trace_keepout
.drc_trace_keepout
Trace Keep Out
object
Stores name of document layer in which all traces keepout areas are stored. Name: .drc_trace_keepout_lyr
.drc_trace_keepout_lyr
Trace Keep Out Layer
product
Defines areas to be used as vias keepout boundaries. Name: .drc_via_keepout
.drc_via_keepout
Via Keep Out
object
Stores name of document layer in which all vias keepout areas are stored. Name: .drc_via_keepout_lyr
.drc_via_keepout_lyr
Via Keep Out Layer
product
Assigned to hole features in drill layers. It defines the type of the drill and is used extensively during fabrication analysis. Name: .drill
.drill
Drill Type
object
A value between 0 - 100000. Name: .drill_flag
.drill_flag
Auto Drill Mgr Flag
object
0
Specifies the drill direction for all drills on a given layer. This information impacts on analysis and potentially on the generation of production tooling information. (default=top2bottom) Name: .drill_layer_direction
.drill_layer_direction
Drill Layer Direction:
layer
top2bottom
Assigned during DXF file input to mark its features as part of a DXF dimension entity. Name: .dxf_dimension
.dxf_dimension
DXF Dimension
object
List of electrical class rules (blank-separated) defining the maximum distance between the two traces of nets considered parallel. Name: .eclass_accumulative_parallel_dist_list
.eclass_accumulative_parallel_dist_list
Accum. Parallel Dist.List
net
List of electrical class rules (blank-separated) defining the maximum distance between the two traces of nets considered parallel. Name: .eclass_accumulative_parallel_max_length_list
.eclass_accumulative_parallel_max_length_list
Accum. Parallel Max.Len.List
net
Electrical class rule. Name: .eclass_impedance
.eclass_impedance
Impedance
net
List of blank-separated electrical class rules. Defines the separation distance within which two traces are considered parallel. Name: .eclass_individual_parallel_dist_list
.eclass_individual_parallel_dist_list
Individ. Parallel Dist.List
net
List of electrical class rules (blank-separated). Defines the maximum length that two nets can run parallel to each other. Name: .eclass_individual_parallel_max_length_list
.eclass_individual_parallel_max_length_list
Individ. Parallel Max. Len. List
net
List of electrical class rules (blank-separated). Defines the distance parallel traces that deviate must maintain the deviation before it is considered a break in parallelism. Name: .eclass_individual_parallel_min_jog_list
.eclass_individual_parallel_min_jog_list
Individ. Parallel Min. Jog List
net
Electrical class rule—high limit of the stub length. Name: .eclass_max_stub_length
.eclass_max_stub_length
Max. Stub Length
net
Maximal number of vias on the nets. Name: .eclass_max_via_count
.eclass_max_via_count
Max. Via Count
net
Electrical class rule—low limit of the stub length. Name: .eclass_min_stub_length
.eclass_min_stub_length
Min. Stub Length
net
Electrical class rule specifying the interval of a rising signal transition(low to high) Name: .eclass_rise_time
.eclass_rise_time
Rise Time
net
Electrical class rule. Name: .eclass_voltage_swing
.eclass_voltage_swing
Voltage Swing
net
Assigns a technology type attribute to an embedded components layer. Name: .ecmp_layer_tech
.ecmp_layer_tech
Embedded Passive Technology
layer
none
Maximum nominal value received at input (its value plus a tolerance). Name: .ecmp_max_value
.ecmp_max_value
Embedded Passive Max. Value
object
Minimum nominal value received at input (its value minus a tolerance). Name: .ecmp_min_value
.ecmp_min_value
Embedded Passive Min. Value
object
Name assigned to an embedded passive feature. Name: .ecmp_name
.ecmp_name
Embedded Passive Name
object
Assigns a component type to an embedded component. Name: .ecmp_type
.ecmp_type
Embedded Passive Type
object
Embedded passive nominal value. For resistors it is the resistance in ohms. Name: .ecmp_value
.ecmp_value
Embedded Passive Nominal Value
object
The engineering change list. Name: .eco
.eco
Engineering Change List
cell
Defines lines controlled by impedance. Lines assigned this attribute are not rerouted nor shaved. Name: .eda_define_imp_line
.eda_define_imp_line
Impedance Line-No Edits
object
Assigns system-generated ID to dimensions. Name: .eda_dimension_id
.eda_dimension_id
Embedded Passive Nominal Value
object
Contains the EDA system layer names that compose a physical layer. It is loaded during the direct EDA translation and is used for graphic synchronization with the EDA system. Name: .eda_layers
.eda_layers
EDA Layers
layer
Electrical class name associating a net with a set of electrical call rules. Electrical class rules include physical and electrical limitations required to assure and analyze the signal integrity of a high speed net. Name: .electrical_class
.electrical_class
Electrical Class
net
A distance value (per layer) to use in netlist adjacency calculation for moving probe testers(currently BSL and PROBOT).
(0.0 to 1000.0; default=20.0) Name: .et_adjacency
.et_adjacency
Adjacency Distance(ET)
layer
20.0
Determines that a feature will be used as an alignment target for PROBOT output Name: .et_align
.et_align
Probot Alignment Targets
object
Assigned to construction features (lines and pads) added to assist in the generation of a rout path. Name: .extended
.extended
Dimension Feature
object
Stores the default DRC area name. This name is applied when no specific area is defined in the DRC map layer, or no such map layer at all. Name: .fab_drc
.fab_drc
Fab DRC
cell
Copper features with this attribute are ignored in analysis actions. (Currently implemented for rout tests only.) Name: .feature_ignore
.feature_ignore
Copper Feature Ignore
object
For a chained feature, this attribute sets the table feed rate when routing. Name: .feed
.feed
Rout Feed Rate
object
Etec Fiducial Output Name: .fiducial_name
.fiducial_name
Etec Fiducial Output
object
This attribute is assigned local fiducial features. It can consist of a list of REFDES (separated by semicolons); a list of the components using this local fiducial. Name: .fiducial_rdlist
.fiducial_rdlist
Local Fiducial Ref.Des.List
object
This attribute is used as the default horizontal distance between apertures when the aperture is used for pattern filling. Name: .fill_dx
.fill_dx
Fill Dx
symbol
0.1
This attribute is used as the default vertical distance between apertures when the aperture is used for pattern filling. Name: .fill_dy
.fill_dy
Fill Dy
symbol
0.1
Indicates the manufacturing direction the PCB will be going through during the flow solder process. Name: .fs_direction_bottom
.fs_direction_bottom
Flow Solder Direction (Bottom)
cell
Indicates the manufacturing direction the PCB will be going through during the flow solder process. Name: .fs_direction_top
.fs_direction_top
Flow Solder Direction (Top)
cell
This is a real value expressing the percent of the value to use as a tolerance (negative tolerance). This is used for all devices: Range of characters : all floating point numbers. Name: .gencad_device_ntol
.gencad_device_ntol
GENCAD Negative Tolerance
component|package
0.0
This is a real value expressing the percent of the value to use as a tolerance (positive tolerance). This is used for all devices : Name: .gencad_device_ptol
.gencad_device_ptol
GENCAD Positive Tolerance
component|package
0.0
This attribute is an enhancement of .gencad_device_type and is used to store the style of the component as defined in GenCAD (such as, NPN, PNP, NFET, PFET, NJFET, PJFET, TTL, CMOS and ECL) Name: .gencad_device_style
.gencad_device_style
GENCAD Device Style
component|package
Stores the type of the component as defined in GenCAD (such as, RES, VRES, DIODE, ZENER, LOGIC, SWITCH, CONN, etc.). Name: .gencad_device_type
.gencad_device_type
GENCAD Device Type
component|package
Stores the electrical value of a component. Name: .gencad_device_value
.gencad_device_value
GENCAD Device Value
component|package
Contains the name of the padstack referenced for this object. Name: .geometry
.geometry
Pad Stack
object
Used during autopanelization to orient the gold plated area toward the extreme side of the panel. Name: .gold_plating
.gold_plating
Gold Plating
object
Type of gold plating used. Name: .gold_plating_defined_by
.gold_plating_defined_by
Gold Plating Defined by
cell
goldmask
Assigned to a component that guards other components. If TRUE, this component is considered a guard component (that is, not likely to be knocked off the board accidentally. To be used in future actions.) Name: .guard_comp
.guard_comp
Component Guard
component|package
no
Assign Object as part of Hatch. Name: .hatch
.hatch
Hatch
object
no
The lines making up the border of a surface. Name: .hatch_border
.hatch_border
Hatch Border
object
no
Assigned to features that are added for partial hatch. The difference between regular hatch and partial hatch is that in partial hatch the cells along the border that intersect the border line are filled; the feature(s) that fill these cells are assigned this attribute. Name: .hatch_serrated_border
.hatch_serrated_border
Hatch Serrated Border
object
no
The attribute defines the type of HDI assembly technology identified in the product model. If None, the special layer is not created. Name: .hdi_assembly_tech
.hdi_assembly_tech
HDI assembly technology
layer
none
Default area name applied to all HDI actions. Name: .hdi_drc
.hdi_drc
HDI Assembly Technology
cell
When this attribute is assigned to a net, it is ignored during Testpoint Allocation Analysis. No potential testpoints are assigned, they are not reported in the Nets without Potential TPs category, the Testpoints Allocation Report, or in Total Number of Nets. Name: .ignore_net
.ignore_net
Ignore Net During Allocation
net
These values are set when inputting Image files into the system. They contain the datum point of an Image user - defined symbol entity used to set the datum when performing output back into Image format. These values should not be changed by the user as this can cause data corruption. Name: .image_dx
.image_dx
Image Dx
symbol
0.0
These values are set when inputting Image files into the system. They contain the datum point of an Image user - defined symbol entity used to set the datum when performing output back into Image format. These values should not be changed by the user as this can cause data corruption. Name: .image_dy
.image_dy
Image Dy
symbol
0.0
For each impedance line bearing this attribute, the system refers to the constraint with the given ID in the impedance constraints table. Name: .imp_constraint_id
.imp_constraint_id
Impedance Constraint ID
object
Assigned to lines that are impedance - controlled. When set, it prevents the lines from being rerouted or thinned during signal layer optimization. Name: .imp_line
.imp_line
Impedance Line
object
Defines a unique ID for all trace segments that are part of the same impedance polyline. Name: .imp_polyline_id
.imp_polyline_id
Impedance Polyline ID
object
Test width of routes used for the provided impedance. Name: .impedance_test_width
.impedance_test_width
Impedance Test Width
layer
0
Indicates that the component requires silkscreen orientation indication. Name: .ind_orient_req
.ind_orient_req
Orientation Indication Required
component|package
no
Contains the name of the file (Gerber, Drill) from which the data was input into the layer. Name: .inp_file
.inp_file
Input File
layer
Defines the end-product class according to IPC-7351. Name: .ipc_class
.ipc_class
IPC Performance Class
product
class1
Assigned to a via drill to indicate one of the IPC-4761 Via types for via tenting, covering, plugging and capping. Refers to the bottom side of the via drill. Name: .ipc_via_type_bottom
.ipc_via_type_bottom
IPC-4761 Bottom Via Type
object
0
Assigned to a via drill to indicate one of the IPC-4761 Via types for via tenting, covering, plugging and capping. Refers to the top side of the via drill. Name: .ipc_via_type_top
Simon Garrison
Included are 350+ attributes available for PCB Assembly and Manufacturing that can be easily changed using the command: Properties...
Here's a quick video no sound) showing how to assign and change any objects attributes.
https://numericalsoftware-update.s3.us-east-1.amazonaws.com/tutorials/2024-07-30_18-25-03_polarity-attributes.mp4
list of all the layers in the
current EDA design.
Name: .all_eda_layers
to remove nonfunctional pads.
Name: .allowed_to_remove_non_functional_pads
size between the drill and the copper of the bottom layer of
the drill span.
Name: .ar_pad_drill_bottom_max
size between the drill and the copper of the bottom layer of
the drill span.
Name: .ar_pad_drill_bottom_min
size between the drill and the copper of an inner layer in
the drill span.
Name: .ar_pad_drill_inner_max
size between the drill and the copper of an inner layer in
the drill span.
Name: .ar_pad_drill_inner_min
size between the drill and the top copper layer in
the drill span.
Name: .ar_pad_drill_top_max
size between the drill and the top copper layer in
the drill span.
Name: .ar_pad_drill_top_min
the maximum annular ring size between the drill and the
soldermask on the bottom layer.
Name: .ar_sm_drill_bottom_max
the minimum annular ring size between the drill and the
soldermask on the bottom layer.
Name: .ar_sm_drill_bottom_min
maximum annular ring size between the drill and the
soldermask on the top layer.
Name: .ar_sm_drill_top_max
minimum annular ring size between the drill and the
soldermask on the top layer.
Name: .ar_sm_drill_top_min
the maximum annular ring size between the drilled pad
of the bottom layer and the soldermask above.
Name: .ar_sm_pad_bottom_max
the minimum annular ring size between the drilled pad
of the bottom layer and the soldermask above.
Name: .ar_sm_pad_bottom_min
maximum annular ring size in between the drilled pad of
the top layer and the soldermask above.
Name: .ar_sm_pad_top_max
minimum annular ring size in between the drilled pad of
the top layer and the solder mask above.
Name: .ar_sm_pad_top_min
Name: .area_name
panel possibly appearing in 180 - degree rotation to itself
Name: .array_with_rotation
belongs (component, package, net, board)
Name: .artwork
Name: .assembly_proc_bottom
Name: .assembly_proc_top
Name: .attrfab_barcode_width
Name: .attrfab_chs
metal layer is to be manufactured on top of the DIELECTRIC material. (optional)
Name: .attrfab_copper_layer_above
metal layer is to be manufactured on bottom of the DIELECTRIC material. (optional)
Name: .attrfab_copper_layer_below
Name: .attrfab_cpn
name as reference in the design application. (optional)
Name: .attrfab_dielectric_material
Name: .attrfab_dsc
Name: .attrfab_ipn
Default: rigid
Name: .attrfab_layer_form
line number and the file name. For example, LNFILE 5 Rev13.v1 indicates that information is
stored in line 5 of file Rev13.v1
Name: .attrfab_lnfile
* qualify status — Whether the part(vendor + mpn) is qualified for production:
-1: Not qualified, 0: Unknown, 1: Qualified.
* chosen status — Whether the part is chosen from among the
alternate parts for the CPN. Only one part can be a chosen part.
0: Not chosen, 1: Chosen
MPN — The manufacturer part number.
For example, MPN 0 Y 4N35S for a CPN component whose
qualification is unknown(0), that is the chosen component(1), with a
manufacturer part number of 4N35S.
Name: .attrfab_mpn
The MPN lines contain these parameters separated by spaces:
* qualify status — Whether the part(vendor + mpn) is qualified for production:
-1: Not qualified, 0: Unknown, 1: Qualified.
* chosen status — Whether the part is chosen from among the
alternate parts for the CPN. Only one part can be a chosen part.
0: Not chosen, 1: Chosen
MPN — The manufacturer part number.
For example, MPN 0 Y 4N35S for a CPN component whose
qualification is unknown(0), that is the chosen component(1), with a
manufacturer part number of 4N35S.
Name: .attrfab_mpn_1
The MPN lines contain these parameters separated by spaces:
* qualify status — Whether the part(vendor + mpn) is qualified for production:
-1: Not qualified, 0: Unknown, 1: Qualified.
* chosen status — Whether the part is chosen from among the
alternate parts for the CPN. Only one part can be a chosen part.
0: Not chosen, 1: Chosen
MPN — The manufacturer part number.
For example, MPN 0 Y 4N35S for a CPN component whose
qualification is unknown(0), that is the chosen component(1), with a
manufacturer part number of 4N35S.
Name: .attrfab_mpn_2
Name: .attrfab_pkg
1: is Top priority
2: Second priority
3:Third priority...so forth
0: Unknown
Name: .attrfab_priority
1: is Top priority
2: Second priority
3:Third priority...so forth
0: Unknown
Name: .attrfab_priority_1
1: is Top priority
2: Second priority
3:Third priority...so forth
0: Unknown
Name: .attrfab_priority_2
Name: .attrfab_qlf
Metal layers for Flex and Rigid-Flex designs. (optional)
Name: .attrfab_reference_layer
Name: .attrfab_vnd
Manufacturer (vendor) name.
Name: .attrfab_vnd_1
Manufacturer (vendor) name.
Name: .attrfab_vnd_2
to original MPN(as determined in BOM Validation).
Name: .attrfab_vpl_mpn
MPN from an external vendor part library corresponding
to original MPN(as determined in BOM Validation).
Name: .attrfab_vpl_mpn_1
MPN from an external vendor part library corresponding
to original MPN(as determined in BOM Validation).
Name: .attrfab_vpl_mpn_2
corresponding to original vendor(as determined in BOM Validation).
Name: .attrfab_vpl_vnd
Manufacturer from an external vendor part library
corresponding to original vendor(as determined in BOM Validation).
Name: .attrfab_vpl_vnd_1
Manufacturer from an external vendor part library
corresponding to original vendor(as determined in BOM Validation).
Name: .attrfab_vpl_vnd_2
machine. Values are translated as 0, 90, 180, 270 degrees.
Name: .axi_direction
penetrated during the backdrill process.
Name: .backdrill_penetrate_stop_layer
to be used for each tool.
Name: .bit
Skip inspection of the step.
gpm: good panel mark. The panel can be
accepted for printing without scanning its
steps for bad board marks.
Name: .board_mark
Name: .board_thickness
Name: .bond_name
Name: .bonding_profile
can be inserted into any line or arc of the rout path.
Name: .break_away
(that was given the attribute .break_away).
Name: .brk_point
semiconductor material.
Name: .bulk_resistivity
to a pad code in the local design.
Name: .cad_local_footprint_change
name of a Cadstar component.
Name: .cad_package_name
data received from the ASSY_PN_OVERRIDE property.
Name: .cad_part_override
to have a fiducial at its center.
Name: .center_fiducial
to the calculated package centroid.
Name: .centroid_correction_x
to the calculated package centroid.
Name: .centroid_correction_y
define the color to be used in plotting a layer in HPGL-1
or 2. The format is rrggbb (where r = red, g = green, b = blue).
Name: .color
Name: .comment
the offset of the cutting tool from the rout path.
Name: .comp
above the board surface.
Name: .comp_height
ID to a component under which there
is an area with space for a shorter component,
and to the feature that defines the area.
Name: .comp_height_area
the CPN package of alternate MPNs)
above the board surface.
Name: .comp_height_max
height, used for calculation of plug-in boards.
Name: .comp_htol_minus
height, used for calculation of plug-in boards.
Name: .comp_htol_plus
on a component during assembly analysis. It is used for printed
components that have no actual body
Name: .comp_ign_spacing
when calculating statistics, or during certain operations,
such as analysis.
Name: .comp_ignore
a surface mount, through-hole mount,
press-fit or other.
Name: .comp_mount_type
on the HDI technology layer.
Name: .comp_name
NON_POLARIZED has no specific pin #1.
Name: .comp_polarity
Name: .comp_type
Name: .comp_type2
The list contains variant names separated by a colon (:)
Name: .comp_variant_list
Name: .comp_weight
to its Units of Measurement.
Name: .copper_weight
Name: .critical_net
a testpoint. If both.non_tp and.critical_tp are assigned
to the same point, .critical_tp takes precedence and the mid point is tested.
In case of a drilled feature the attribute must be added to the drill hole.
Name: .critical_tp
current variant for a step.
Name: .current_variant
whom the product model was created.
Name: .customer
of film layers by the film optimization algorithm.
Name: .cut_line
For example, Cadence, Mentor.
Name: .data_source
Name: .desc1
Name: .desc10
Name: .desc2
Name: .desc3
Name: .desc4
Name: .desc5
Name: .desc6
Name: .desc7
Name: .desc8
Name: .desc9
the product model originated.
Name: .design_center
Name: .design_origin_x
Name: .design_origin_y
and is used to store the style of the component as defined
in GenCAD (such as, NPN, PNP, NFET, PFET, NJFET,
PJFET, TTL, CMOS and ECL).
Name: .device_style
device(such as, RES, VRES, DIODE, ZENER, LOGIC,
SWITCH, CONN, etc.).
Name: .device_type
Name: .device_value
value to use as a tolerance (negative tolerance). This is
used for all devices. Range of characters : all floating point numbers.
Name: .device_value_ntol
value to use as a tolerance (positive tolerance). This is
used for all devices. Range of characters : all floating point numbers.
Name: .device_value_ptol
dielectric(Eo) to the net field(E)
with dielectric. It is unitless and
has a range value of 1 for metals.
Typical values are 4 and 5.
(0.0 to 1000.0; default = 0.0)
Name: .dielectric_constant
must be routed together.
Name: .diff_pair
between differential pair nets.
Name: .dpair_gap
to Top, Bottom, or Both component layers.
Name: .drc_assembly_lyrs
defined for the whole board.
Name: .drc_board
to a keepin/keepout area.
Name: .drc_comp_height
height restriction keepin/keepout areas are stored.
Name: .drc_comp_height_lyr
component placement keepin boundary.
Name: .drc_comp_keepin
which all component keepin areas are stored.
Name: .drc_comp_keepin_lyr
component placement keepout boundary.
Name: .drc_comp_keepout
which all component keepout areas are stored.
Name: .drc_comp_keepout_lyr
User-defined attribute for user to specify name of
layers in which to activate keepin / keepout areas
Name: .drc_etch_lyrs
as effective on all layers.
Name: .drc_etch_lyrs_all
Allows the keepin/keepout area to apply only to specified board layers.
The attribute's length is equal to the number of board layers.
0=ignore layer, 1=activate areas in that layer.
Name: .drc_etch_lyrs_bit
to be allowed in a height restriction area.
Name: .drc_max_height
Name: .drc_mech
to be allowed in a height restriction area.
Name: .drc_min_height
as pads keepout boundary.
Name: .drc_pad_keepout
keepout areas are stored. Default as defined in the
drc_pad_keepout configuration parameter.
Name: .drc_pad_keepout_lyr
planes keepout boundary.
Name: .drc_plane_keepout
keepout areas are stored.
Name: .drc_plane_keepout_lyr
Name: .drc_ref_des
(rout = lines, arcs, vias, pads and surfaces on signal and/or
power and ground layers).
Name: .drc_route_keepin
all rout keepin areas are stored.
Name: .drc_route_keepin_lyr
(rout = lines, arcs, vias, pads and surfaces on signal and/or
power and ground layers).
Name: .drc_route_keepout
all rout keepout areas are stored.
Name: .drc_route_keepout_lyr
keepin area boundaries.
Name: .drc_tp_keepin
all testpoint keepin areas are stored.
Name: .drc_tp_keepin_lyr
keepout area boundaries.
Name: .drc_tp_keepout
all testpoint keepout areas are stored.
Name: .drc_tp_keepout_lyr
(traces=lines and arcs on signal and/or power and ground layers).
Name: .drc_trace_keepout
all traces keepout areas are stored.
Name: .drc_trace_keepout_lyr
vias keepout boundaries.
Name: .drc_via_keepout
all vias keepout areas are stored.
Name: .drc_via_keepout_lyr
It defines the type of the drill and is used
extensively during fabrication analysis.
Name: .drill
Name: .drill_flag
on a given layer. This information impacts on
analysis and potentially on the generation
of production tooling information.
(default=top2bottom)
Name: .drill_layer_direction
features as part of a DXF dimension entity.
Name: .dxf_dimension
the maximum distance between the two traces of
nets considered parallel.
Name: .eclass_accumulative_parallel_dist_list
the maximum distance between the two traces of
nets considered parallel.
Name: .eclass_accumulative_parallel_max_length_list
Name: .eclass_impedance
the separation distance within which two traces are considered parallel.
Name: .eclass_individual_parallel_dist_list
the maximum length that two nets can run parallel to each other.
Name: .eclass_individual_parallel_max_length_list
the distance parallel traces that deviate must maintain
the deviation before it is considered a break in parallelism.
Name: .eclass_individual_parallel_min_jog_list
Name: .eclass_max_stub_length
Name: .eclass_max_via_count
Name: .eclass_min_stub_length
rising signal transition(low to high)
Name: .eclass_rise_time
Name: .eclass_voltage_swing
an embedded components layer.
Name: .ecmp_layer_tech
(its value plus a tolerance).
Name: .ecmp_max_value
(its value minus a tolerance).
Name: .ecmp_min_value
embedded passive feature.
Name: .ecmp_name
an embedded component.
Name: .ecmp_type
For resistors it is the resistance in ohms.
Name: .ecmp_value
Name: .eco
this attribute are not rerouted nor shaved.
Name: .eda_define_imp_line
Name: .eda_dimension_id
It is loaded during the direct EDA translation and is used for
graphic synchronization with the EDA system.
Name: .eda_layers
electrical call rules. Electrical class rules include
physical and electrical limitations required to assure
and analyze the signal integrity of a high speed net.
Name: .electrical_class
netlist adjacency calculation for moving probe
testers(currently BSL and PROBOT).
(0.0 to 1000.0; default=20.0)
Name: .et_adjacency
as an alignment target for PROBOT output
Name: .et_align
(lines and pads) added to assist in the
generation of a rout path.
Name: .extended
when no specific area is defined in the DRC map
layer, or no such map layer at all.
Name: .fab_drc
analysis actions. (Currently implemented for rout tests only.)
Name: .feature_ignore
sets the table feed rate when routing.
Name: .feed
Name: .fiducial_name
consist of a list of REFDES (separated by semicolons); a
list of the components using this local fiducial.
Name: .fiducial_rdlist
between apertures when the aperture is used for pattern filling.
Name: .fill_dx
between apertures when the aperture is used for pattern filling.
Name: .fill_dy
going through during the flow solder process.
Name: .fs_direction_bottom
going through during the flow solder process.
Name: .fs_direction_top
value to use as a tolerance (negative tolerance). This is
used for all devices: Range of characters : all floating point numbers.
Name: .gencad_device_ntol
value to use as a tolerance (positive tolerance). This is
used for all devices :
Name: .gencad_device_ptol
used to store the style of the component as defined in
GenCAD (such as, NPN, PNP, NFET, PFET, NJFET,
PJFET, TTL, CMOS and ECL)
Name: .gencad_device_style
(such as, RES, VRES, DIODE, ZENER, LOGIC, SWITCH, CONN, etc.).
Name: .gencad_device_type
Name: .gencad_device_value
referenced for this object.
Name: .geometry
gold plated area toward the extreme side of the panel.
Name: .gold_plating
Name: .gold_plating_defined_by
components. If TRUE, this component is considered a guard component
(that is, not likely to be knocked off the board accidentally.
To be used in future actions.)
Name: .guard_comp
Name: .hatch
Name: .hatch_border
difference between regular hatch and partial hatch is that
in partial hatch the cells along the border that
intersect the border line are filled; the feature(s) that fill
these cells are assigned this attribute.
Name: .hatch_serrated_border
assembly technology identified in the product model.
If None, the special layer is not created.
Name: .hdi_assembly_tech
Name: .hdi_drc
ignored during Testpoint Allocation Analysis. No
potential testpoints are assigned, they are not
reported in the Nets without Potential TPs category, the
Testpoints Allocation Report, or in Total Number of Nets.
Name: .ignore_net
system. They contain the datum point of an Image
user - defined symbol entity used to set the datum when
performing output back into Image format. These values
should not be changed by the user as this can cause data corruption.
Name: .image_dx
system. They contain the datum point of an Image
user - defined symbol entity used to set the datum when
performing output back into Image format. These values
should not be changed by the user as this can cause data corruption.
Name: .image_dy
the system refers to the constraint with
the given ID in the impedance constraints table.
Name: .imp_constraint_id
set, it prevents the lines from being rerouted or thinned
during signal layer optimization.
Name: .imp_line
segments that are part of
the same impedance polyline.
Name: .imp_polyline_id
the provided impedance.
Name: .impedance_test_width
silkscreen orientation indication.
Name: .ind_orient_req
from which the data was input into the layer.
Name: .inp_file
class according to IPC-7351.
Name: .ipc_class
Via types for via tenting, covering, plugging and
capping. Refers to the bottom side of the via drill.
Name: .ipc_via_type_bottom
Via types for via tenting, covering, plugging and
capping. Refers to the top side of the via drill.
Name: .ipc_via_type_top